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44 - pin plastic 7mm x 7mm chip-scale package (qfn) features arinc 429 compliant single 3.3v power supply directly to arinc 429 bus programmable label recognition for 256 labels 32 x 32 receive fifos and priority-label buffers 10mhz, four-wire serial peripheral interface (spi) industrial & extended temperature ranges specification on-chip analog line driver and receiver connect independent data rates for transmit and receive general description the hi-3593 from holt integrated circuits is a cmos integrated circuit for interfacing a serial peripheral interface (spi) enabled microcontroller to the arinc 429 serial bus. the device provides two receivers, each with user-programmable label recognition for any combination of 256 possible labels, 32 x 32 receive fifo, 3 priority- label quick-access double-buffered registers and analog line receiver. the independent transmitter has a 32 x 32 transmit fifo and built-in line driver. the line driver operates from a single 3.3v supply and includes on-chip dc/dc converter to generate the bipolar arinc 429 differential voltage levels needed to directly drive the arinc 429 bus. the status of the transmit and receive fifos and priority-label buffers can be monitored using the programmable external interrupt pins, or by polling the hi-3593 status registers. other features include a programmable option of data or parity in the 32nd bit, and the ability to switch the bit-signifiance of arinc 429 labels. pins are available with different input resistance and output resistance values which provides flexibility when using external lightning protection circuitry. the serial peripheral interface minimizes the number of host interface signals resulting in a small footprint device that can be interfaced to a wide range of industry-standard microcontrollers supporting spi. alternatively, the spi signals may be controlled using just four general purpose i/o port pins from a microcontroller or custom fpga. the spi and all control signals are cmos and ttl compatible and support 3.3v operation. the hi-3593 applies the arinc 429 protocol to the receivers and transmitter. arinc 429 databus timing comes from a 1 mhz clock input, or an internal counter can derive it from higher clock frequencies having certain fixed values, possibly the external host processor clock. pin configurations (top view) 44 - pin plastic quad flat pack (pqfp) 3.3v arinc 429 dual receiver, single transmitter with spi interface august 2013 hi-3593 (ds3593 rev. b) 08/13 44 - vdd 43 - vdd 42 - cp- 41 - cp+ 40 - v+ 39 - gnd 38 - gnd 37 - cn+ 36 - cn- 35 - v- 34 - 33 - ampa 32 - txaout 31 - ampb 30 - txbout 29 - 28 - tfull 27 - tempty 26 - r1flag 25 - r1int 24 - r2flag 23 - r2int cs-12 si-13 sck-14 so-15 gnd-16 mb1-1 - 17 mb1-2 - 18 mb1-3 - 19 mb2-1 - 20 mb2-2 - 21 mb2-3 - 22 -1 rin1a-40 - 2 rin1a - 3 rin1b - 4 rin1b-40 - 5 rin2a-40 - 6 rin2a - 7 rin2b - 8 rin2b-40 - 9 mr-10 aclk - 11 hi-3593pqi hi-3593pqt hi-3593pqm 44 - vdd 43 - vdd 42 - cp- 41 - cp+ 40 - v+ 39 - gnd 38 - gnd 37 - cn+ 36 - cn- 35 - v- 34 - -1 rin1a-40 - 2 rin1a - 3 rin1b - 4 rin1b-40 - 5 rin2a-40 - 6 rin2a - 7 rin2b - 8 rin2b-40 - 9 mr - 10 aclk - 11 33 - ampa 32 - txaout 31 - ampb 30 - txbout 29 - 28 - tfull 27 - tempty 26 - r1flag 25 - r1int 24 - r2flag 23 - r2int -12 si - 13 sck - 14 so - 15 gnd - 16 mb1-1 - 17 mb1-2 - 18 mb1-3 - 19 mb2-1 - 20 mb2-2 - 21 mb2-3 - 22 cs HI-3593PCI hi-3593pct hi-3593pcm holt integrated circuits www.holtic.com
vdd (3.3v) ampa ampb spi interface txaout txbout receive control receive status arinc 429 transmit data fifo arinc 429 transmit formatter arinc 429 line driver arinc 429 received data fifo (32 x 32) label filter arinc 429 valid word checker (see fig. 3) arinc 429 line receiver label filter bit map memory rin1b-40 rin1a rin1b rin1a-40 sck cs si so v- aclk gnd tfull v+ 40 k 40 k 37.5 arinc clock divider block diagram hi-3593 holt integrated circuits 2 priority - label match (x3) p-l reg 3 p-l reg 2 p-l reg 1 receiver 1 receiver 2 rin2b-40 rin2a rin2b rin2a-40 dc / dc converter 3.3v transmitter v+ v- cp+ cp- cn+ cn- mr v+ v- transmit control transmit status buffer buffer buffer flag / interrupt r1flag r1int r2flag r2int tempty mb2-3 mb2-2 mb2-1 mb1-3 mb1-2 mb1-1 5 37.5 5 47uf 47uf 0.47uf 2.2uf
signal function description internal pull up / down rin1a-40 input alternate arinc receiver 1 positive input. requires external 40k ohm resistor rin1a input arinc receiver 1 positive input. direct connection to arinc 429 bus rin1b input arinc receiver 1 negative input. direct connection to arinc 429 bus rin1b-40 input alternate arinc receiver 1 negative input. requires external 40k ohm resistor rin2a-40 input alternate arinc receiver 2 positive input. requires external 40k ohm resistor rin2a input arinc receiver 2 positive input. direct connection to arinc 429 bus rin2b input arinc receiver 2 negative input. direct connection to arinc 429 bus rin2b-40 input alternate arinc receiver 2 negative input. requires external 40k ohm resistor mr input master reset. a positive pulse clears receive and transmit data fifos and flags 50k ohm pull-down aclk input master timing source for the arinc 429 receiver and transmitter 50k ohm pull-down input chip select. data is shifted into si and out of so when is low. 50k ohm pull-up si input spi interface serial data input 50k ohm pull-down sclk input spi clock. data is shifted into or out of the spi interface using sck 50k ohm pull-down so output spi interface serial data output gnd power chip 0v supply mb1-1 output goes high when receiver 1, priority-label mail box 1 contains a message mb1-2 output goes high when receiver 1, priority-label mail box 2 contains a message mb1-3 output goes high when receiver 1, priority-label mail box 3 contains a message mb2-1 output goes high when receiver 2, priority-label mail box 1 contains a message mb2-2 output goes high when receiver 2, priority-label mail box 2 contains a message mb2-3 output goes high when receiver 2, priority-label mail box 3 contains a message r2int output receiver 2 programmable interrupt pin r2flag output goes high as defined by flag / interrupt assignment register r1int output receiver 1 programmable interrupt pin r1flag output goes high as defined by flag / interrupt assignment register tempty output goes high when the transmit fifo is empty tfull output goes high when the transmit fifo contains the maximum 32 arinc 429 words txbout output arinc line driver negative output. direct connection to arinc 429 bus ampb output alternate arinc line driver negative output. requires external 32.5 ohm resistor txaout output arinc line driver positive output. direct connection to arinc 429 bus ampa output alternate arinc line driver positive output. requires external 32.5 ohm resistor v- converter dc/dc negative voltage output cn- converter dc/dc converter fly capacitor for v- cn+ converter dc/dc converter fly capacitor for v- v+ converter dc/dc positive voltage output cp- converter dc/dc converter fly capacitor for v+ cp+ converter dc/dc converter fly capacitor for v+ vdd power chip 3.3v supply cs cs pin descriptions holt integrated circuits 3 hi-3593 instructions instruction op codes are used to read, write and configure the hi- 3593. when goes low, the next 8 clocks at the sck pin shift an instruction op code into the decoder, starting with the first rising edge. the op code is fed into the si pin, most significant bit first. for write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising sck edge. data word length varies depending on word type written: 8-bit control register writes, 32- bit arinc label writes or 256-bit writes to a channel?s label- matching enable/disable memory. cs for read instructions, the most significant bit of the requested data word appears at the so pin after the last op code bit is clocked into the decoder, at the next falling sck edge. as in write instructions, the data field bit-length varies with read instruction type. spi instructions are of a common format. the first bit specifies whether the instruction is a write ?0? or read ?1? transfer. the next five bits specify the source or destination of the associated data byte(s), and the last two bits are ?don?t care?. spi instruction format 76543210 msb lsb source / destination x x r/w
table 1. defined instructions op-code r/w # data description bytes 0x00 w 0 instruction not implemented. no operation. 0x04 w 0 software controlled master reset 0x08 w 1 write transmit control register 0x0c w 4 write arinc 429 message to transmit fifo 0x18 w 3 write receiver 1 priority-label match registers. the data field consists of three eight-bit labels. the first data byte is written to p-l filter #3, the second to p-l filter #2, and the last byte to filter #1 0x10 w 1 write receiver 1 control register 0x14 w 32 write label values to receiver 1 label memory. starting with label 0xff, consecutively set or reset each label in descending order. for example, if the first data byte is programmed to 10110010 then labels ff, fd fc and f9 will be set and fe, fb, fa and f8 will be reset. 0x24 w 1 write receiver 2 control register 0x28 w 32 write label values to receiver 2 label memory. starting with label 0xff, consecutively set or reset each label in descending order. for example, if the first data byte is programmed to 10110010 then labels ff, fd fc and f9 will be set and fe, fb, fa and f8 will be reset. 0x2c w 3 write receiver 2 priority-label match registers. the data field consists of three eight-bit labels. the first eight bits is written to p-l filter #3, the second to p-l filter #2, and the last byte to filter #1 0x34 w 1 write flag / interrupt assignment register 0x38 w 1 write aclk division register 0x40 w 0 transmit current contents of transmit fifo if transmit control register bit 5 (tmode) is a ?0? 0x44 w 0 software reset. clears the transmit and receive fifos and the priority-label registers 0x48 w 0 set all bits in receiver 1 label memory to a ?1? 0x4c w 0 set all bits in receiver 2 label memory to a ?1? 0x80 r 1 read transmit status register 0x84 r 1 read transmit control register 0x90 r 1 read receiver 1 status register 0x94 r 1 read receiver 1 control register 0x98 r 32 read label values from receiver 1 label memory. 0x9c r 3 read receiver 1 priority-label match registers. 0xa0 r 4 read one arinc 429 message from the receiver 1 fifo 0xa4 r 3 read receiver 1 priority-label register #1, arinc429 bytes 2, 3 & 4 (bit s9-32) 0xa8 r 3 read receiver 1 priority-label register #2, arinc429 bytes 2, 3 & 4 (bit s9-32) 0xac r 3 read receiver 1 priority-label register #3, arinc429 bytes 2, 3 & 4 (bit s9-32) 0xb0 r 1 read receiver 2 status register 0xb4 r 1 read receiver 2 control register 0xb8 r 32 read label values from receiver 2 label memory. 0xbc r 3 read receiver 2 priority-label match registers. 0xc0 r 4 read one arinc 429 message from the receiver 2 fifo 0xc4 r 3 read receiver 2 priority-label register #1, arinc429 bytes 2, 3 & 4 (bit s9-32) 0xc8 r 3 read receiver 2 priority-label register #2, arinc429 bytes 2, 3 & 4 (bit s9-32) 0xcc r 3 read receiver 2 priority-label register #3, arinc429 bytes 2, 3 & 4 (bit s9-32) 0xd0 r 1 read flag / interrupt assignment register 0xd4 r 1 read aclk division register 0xff r 0 instruction not implemented. no operation. hi-3593 holt integrated circuits 4
hi-3593 holt integrated circuits 5 bit name 7 rflip 6 sd9 5 sd10 4 sdon r/w 3 parity 2 labrec 1 plon 0rate r/w default description r/w 0 setting this bit reverses the bit order of the first 8 bits of each arinc 429 message received. see figure 1 for details. r/w 0 if the receiver decoder is enable by setting the sdon bit to a ?1?, then arinc 429 message bit 9 must match this bit for the message to be accepted. r/w 0 if the receiver decoder is enable by setting the sdon bit to a ?1?, then arinc 429 message bit 10 must match this bit for the message to be accepted. 0 if this bit is set, bits 9 and 10 of the received arinc 429 message must match sd9 and sd10 r/w 0 received word parity checking is enabled when this bit is set. if ?0?, all 32 bits of the received arinc 429 word are stored without parity checking. r/w 0 when ?0?, all received messages are stored. if this bit is set, incoming arinc message label filtering is enabled. only messages whose corresponding label filter table entry is set to a ?1? will be stored in the receive fifo. r/w 0 priority-label register enable. if plon = ?1? the three priority-label registers are enabled and received arinc 429 messages with labels that match one of the three pre-programmed values will be capured and stored in the corresponding prioty-label mail boxes. if plon = ?0? the priority-label matching feature is turned off and no words are placed in the mail boxes. r/w 0 if rate is ?0?, arinc 429 high-speed data rate is selected. rate = ?1? selects low-speed arinc 429 data rate (high-speed / 8). 76543210 msb lsb sdon parity labrec plon rate sd10 sd9 rflip receive control register (receiver 1 write, spi op-code 0x10) (receiver 1 read, spi op-code 0x94) (receiver 2 write, spi op-code 0x24) (receiver 2 read, spi op-code 0xb4) bit name 7 hiz 6 tflip 5 tmode 4 selftest r/w 3 oddeven 2 tparity 1x 0rate r/w default description r/w 0 setting this bit puts the on-chip line driver outputs to a high-impedance state. r/w 0 setting this bit reverses the bit order of the first 8 bits of each arinc 429 message transmitted. see figure 1 for details. r/w 0 if tmode is ?0?, data in the transmit fifo is sent to the arinc 429 bus only upon receipt of an spi op-code 0x40, transmit enable, command. if tmode is a ?1?, data is sent as soon as it is available. 0 setting selftest causes an internal connection to be made looping-back the transmitter outputs to both receiver inputs for self-test purposes. when in self-test mode, the hi-3593 ignores data received on the two arinc 429 receive channels and holds the on-chip line driver outputs in the null state to prevent self-test data being transmitted to other receivers on the bus. r/w 0 if the tparity bit is set, the transmitter inserts an odd parity bit if oddeven = ?0?, or an even if oddeven = ?1?. r/w 0 if tparity = ?0?, no parity bit is inserted and the 32nd transmitted bit is data. when tparity is a ?1? a parity bit is substituted for bit 32 according to the oddeven bit value. r/w 0 not used. r/w 0 if rate is ?0?, arinc 429 high-speed data rate is selected. rate = ?1? selects low-speed arinc 429 data rate (high-speed / 8). 76543210 msb lsb selftest oddeven tparity x rate tmode tflip hiz transmit control register (write, spi op-code 0x08) (read, spi op-code 0x84) register descriptions
holt integrated circuits 6 hi-3593 bit name 7x 6x 5 pl3 4 3 2 fffull 1 ffhalf 0 ffempty r/w default description r 0 not used. always reads ?0? r 0 not used. always reads ?0? r 0 this bit is set when a message is received by priority label filter #3 pl2 r 0 this bit is set when a message is received by priority label filter #2 pl1 r 0 this bit is set when a message is received by priority label filter #1 r 0 this bit is set when the receive fifo contains 32 arinc 429 messages r 0 this bit is set when the receive fifo contains at least 16 arinc 429 messages r 1 this bit is set when the receive fifo is empty 76543210 msb lsb pl2 pl1 fffull ffhalf ffempty pl3 x x receive status register (receiver 1 read, spi op-code 0x90) (receiver 2 read, spi op-code 0xb0) bit name 7x 6x 5x 4x r 3x 2 tffull 1 tfhalf 0 tfempty r/w default description r 0 not used. always reads ?0? r 0 not used. always reads ?0? r 0 not used. always reads ?0? 0 not used. always reads ?0? r 0 not used. always reads ?0? r 0 this bit is set when the transmit fifo contains 32 arinc 429 messages r 0 this bit is set when the transmit fifo contains at least 16 arinc 429 messages r 1 this bit is set when the transmit fifo is empty 76543210 msb lsb x x tffull tfhalf tfempty x x x transmit status register (read, spi op-code 0x80) 0 0 0 0 0 bit name 7x 6x 5x 4 - 1 div[3:0] r/w 0x r/w default description r/w 0 not used. r/w 0 not used. r/w 0 not used. 0 the value programmed in div[3:0] sets the aclk division ratio (see table 2) r/w 0 not used. 76543210 msb lsb div[3] div[2] div[1] div[0] x x x x aclk division register (write, spi op-code 0x38) (read, spi op-code 0xd4) 0 0 0 00 0
holt integrated circuits 7 hi-3593 bit name 7-6 r2int[1:0] 5-4 r2flag[1:0] 1-0 r1flag[1:0] r/w r/w default description r/w 0 the value of r2int[1:0] defines the function of the r2int output pin, as follows: 00 r2int pulses high when a valid message is received and placed in the receiver 2 fifo or any of the receiver 2 priority- label mail boxes 01 r2int pulses high when a message is received in receiver 2 priority-label mail box #1 10 r2int pulses high when a message is received in receiver 2 priority-label mail box #2 11 r2int pulses high when a message is received in receiver 2 priority-label mail box #3 r/w 0 the value of r2flag[1:0] defines the function of the r2flag output pin, as follows: 00 r2flag goes high when receiver 2 fifo is empty 01 r2flag goes high when receiver 2 fifo contains 32 arinc 429 words (fifo is full) 10 r2flag goes high when receiver 2 fifo contains at least sixteen arinc 429 words (fifo is half-full) 11 r2flag goes high when receiver 2 fifo contains one or more words (fifo is not empty) 3-2 r1int[1:0] r/w 0 the value of r1int[1:0] defines the function of the r1int output pin, as follows: 00 r1int pulses high when a valid message is received and placed in the receiver 1 fifo or any of the receiver 1 priority- label mail boxes 01 r1int pulses high when a message is received in receiver 1 priority-label mail box #1 10 r1int pulses high when a message is received in receiver 1 priority-label mail box #2 11 r1int pulses high when a message is received in receiver 1 priority-label mail box #3 0 the value of r1flag[1:0] defines the function of the r1flag output pin, as follows: 00 r1flag goes high when receiver 1 fifo is empty 01 r1flag goes high when receiver 1 fifo contains 32 arinc 429 words (fifo is full) 10 r1flag goes high when receiver 1 fifo contains at least sixteen arinc 429 words (fifo is half-full) 11 r1flag goes high when receiver 1 fifo contains one or more words (fifo is not empty) 76543210 msb lsb r2flag[0] r1int[1] r1int[0] r1flag[1] r1flag[0] r2flag[1] r2int[0] r2int[1] flag / interrupt assignment register (write, spi op-code 0x34) (read, spi op-code 0xd0)
arinc 429 bit ordering arinc 429 messages consist of a 32-bit sequence as shown below. the first eight bits that appear on the arinc 429 bus are the label byte. the next twenty three bits comprise a data field which presents data in a variety of formats defined in the arinc 429 specification. the last bit transmitted is an odd parity bit. arinc 429 data is transmitted between the hi-3593 and host microcontroller using the four-wire serial peripheral interface (spi). a read or write operation consists of a single-byte op-code followed by the data. when writing to the transmit fifo or reading from the receive fifos, the spi data field is four bytes. figure 1 shows how the spi data bytes are mapped to the arinc 429 message. arinc 429 specifies the msb of the label as arinc bit 1. conversely, the data field msb is bit 31. so the bit significance of the label byte and data fields are opposite. the hi-3593 may be programmed to ?flip? the bit ordering of the label byte as soon as it is received and immediately prior to transmission. this is accomplished by setting the tflip bit to a ?1? in the transmit control register and/or the rflip bit in the receive control registers. the rflip bit does not control priority label match registers. note that when reading arinc 429 messages from the priority- label registers the label byte is omitted to permit a faster read time. the label value will match the value loaded into the match register and therefore does not need to be output each time a message is read. 7 6 5 4 3 2 1 8 lsb arinc 429 message as received / transmitted on the arinc 429 serial bus 12 13 16 18 19 sdi 22 23 27 31 parity label data msb lsb msb time arinc 429 message as transferred on the spi bus hi-3593 holt integrated circuits 8 15 14 11 10 9 21 20 28 25 32 17 24 26 29 30 sdi 0 29 28 25 23 22 sdi 19 18 14 10 parity spi op-code data msb lsb 26 27 30 31 32 20 21 13 16 9 24 17 15 12 11 6 2 5 8 1 7 4 3 example 1. write transmit fifo (op-code 0x0c) with tflip bit = ?0?. 000 11 00 sdi label lsb msb 29 28 25 23 22 sdi 19 18 14 10 parity spi op-code data msb lsb 26 27 30 31 32 20 21 13 16 9 24 17 15 12 11 6 2 5 8 1 7 4 3 example 2. read receiver 1 fifo (op-code 0xa0) with rflip bit = ?1?. 00 1 00 sdi label msb lsb 1 00 29 28 25 23 22 sdi 19 18 14 10 parity spi op-code data msb lsb 26 27 30 31 32 20 21 13 16 9 24 17 15 12 11 example 3. read receiver 2 priority-label register #3 (op-code 0xcc). 0 1 00 sdi 1 0 11 spi op-code example 4. write receiver 2 priority-label match registers (op-code 0x2c)with rflip bit = ?1? or ?0?. 000 1 0 11 0 label #1 msb lsb label #2 msb lsb label #3 msb lsb 8 7 6 5 4 3 2 1 1 12 2 3 3 4 4 5 5 6 67 78 8 figure 1. arinc 429 & spi bit ordering
initialization the hi-3593 may be initialized using the master reset (mr) pin or under software control by executing spi op-code 0x04. mr must be pulsed high for 1 to bring the part to its completely reset state. mr clears all three fifos, all six priority-label mail boxes, clears the filter memories and match registers and sets all other internal registers to their default state. software reset is performed using spi op-code 0x44. software reset clears all three fifos and all six priority-label mail boxes, but does not affect the values stored in the filter memories, priority-label match registers or other writeable registers. the transmit and receive status registers will reflect the state of the post-software reset device. s for correct arinc 429 data rate transmission and reception, and bit timing, the hi-3593 transmit and receive logic requires a 1 mhz +/- 1% reference clock source. the clock is input at the aclk pin and must be 1 mhz or any even multiple of 1 mhz up to 30 mhz. if a clock source greater than 1 mhz is used, then the aclk division register must be programmed with the appropriate scaling value. note that the least significant bit of the aclk division register is fixed at ?0? allowing only even numbers to be programmed. similarly the three most significant bits are also fixed at ?0? limiting the maximum value to 0x1e. the aclk division register is cleared to 0x00 after master reset and is unaffected by software reset. when programmed to 0x00, the aclk division ratio is one, and a 1 mhz clock should be applied to aclk. the aclk division register is loaded using spi op-code 0x38 and read using op- code 0xd4. the following table provides examples of aclk frequency and aclk division register values for correct arinc 429 operation: clock frequency selection arinc 429 receivers the hi-3593 has two completely independent arinc 429 receive channels. each channel has an on-chip analog line receiver for connection to the arinc 429 incoming data bus. the arinc 429 specification requires the following detection levels: one +6.5 volts to +13 volts null +2.5 volts to -2.5 volts zero -6.5 volts to -13 volts the hi-3593 guarantees recognition of these levels with a common mode voltage with respect to gnd less than 30v for the worst case condition (3.15v supply and 13v signal level). design tolerances guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the arinc signal (including nulls) is outside the differential voltage ranges, the hi- 3593 receiver rejects the data. the arinc 429 specification defines the following timing toler- ances for received data: (rate = ?0?) (rate = ?1?) bit rate 100k bps 1% 12k -14.5k bps pulse rise time 1.5 0.5 sec 10 5 sec pulse fall time 1.5 0.5 sec 10 5 sec pulse width 5 sec 5% 34.5 to 41.7 sec the hi-3593 accepts signals within these tolerances and rejects signals outside these tolerances. receiver logic achieves this as described below: 1. an accurate 1mhz clock source is required to validate the receive signal timing. 2. the receiver uses three separate 10-bit sampling shift reg- isters for ones detection, zeros detection and null detection. when the input signal is within the differential voltage range for any shift register?s state (one, zero or null) sampling clocks a ?1? into that register. when the receive signal is out- side the differential voltage range defined for any shift regis- ter, a ?0? is clocked. only one shift register can clock a ?1? for any given sample. all three registers clock zeros if the differ- ential input voltage is between defined state voltage bands. valid data bits require at least three consecutive one or zero samples (three ?1?s?) in the first five positions of the ones or zeros sampling shift register, and at least three consecutive null samples (three ?1?s?) in the second five positions of the null sampling shift register within the data bit interval. a word gap null requires at least three consecutive null sam- ples in the first half of the null sampling shift register and at least three consecutive null samples in the second half of the null sampling shift register. this guarantees the minimum pulse width. state differential voltage high speed low speed bit timing functional description holt integrated circuits 9 hi-3593 configuration the transmit control register and receiver control registers are used to configure the arinc 429 transmission channel and two arinc 429 receive channels. the registers may be written or read at any time. they are reset to 0x00 following master reset and are unchanged by software reset. refer to the receiver control register and transmit control register descriptions for detailed information. aclk division register value external clock 0x00 1 mhz 0x02 2 mhz 0x04 4 mhz 0x06 6 mhz 0x08 8 mhz 0x0a 10 mhz ?? ?? 0x1c 28 mhz 0x1e 30 mhz table 2. aclk division
all three priority-label match registers are loaded using spi op- code 0x18 (receiver 1) or 0x2c (receiver 2), followed by three label match values. the first byte is the match value for priority-label register #3, the second for priority-label register #2 and the third for priority-label #1. the match values may be checked by reading the priority-label match registers using spi op-code 0x9c (receiver 1) or 0xbc (receiver 2). when using the priority-label feature, all three priority-label match registers must be loaded to avoid unintended matches occurring on un-programmed priority-label match register random values. if less than three priority-labels are required for a particular application, duplicate copies of the same match value should be stored in two (or three) registers. note that priority-label registers (mail boxes) are only 24 bits long. because the arinc 429 label byte value is pre-programmed for each register it is not necessary to store it when words are received. this allows a shorter and faster access of the data field using spi op-codes 0xa4, 0xa8 and 0xac (receiver 1 priority-label registers #1, #2 and #3) or 0xc4, 0xc8 and 0xcc (receiver 2 priority-label registers #1, #2 and #3). the receive status register bits pl1, pl2 and pl3 indicate when priority-label data is available in the priority-label registers. six status output pins mb1-1 through mb2-3 also indicate when data is available at each of the six priority-label registers. the r1int and r2int interrupt pins can also be triggered when priority labels are captured by programming bits 7, 6, 3 and 2 of the flag / interrupt assignment register. functional description (cont.) differential amplifiers comparators figure 2. arinc receiver input rina-40 rina rinb rinb-40 vdd gnd vdd gnd one null zero holt integrated circuits 10 3. to validate the receive data bit rate, each bit must follow its preceding bit by not less than 8 samples and not more than 12 samples. with exactly 1mhz input clock frequency, the acceptable data bit rates are: 83k bps 10.4k bps 125k bps 15.6k bps 4. following the last data bit of a valid reception, the word gap timer samples the null shift register every 10 input clocks (every 80 clocks for low speed). if a null is present, the word gap counter is incremented. a word gap count of 3 enables the next reception. receiver parity checking is enabled by setting the receive control register parity bit to a ?1?. when enabled, the receiver parity circuit counts ones received, including the parity bit. if the result is odd, a "0" is stored in the 32nd bit position, overwriting the received parity bit. the ?0? indicates a parity bit check pass. if receive parity is enabled and a word is received with bad odd parity, the 32nd bit is overwritten with a ?1? indicating a parity check fail. when the receiver control register parity bit is a ?0?, no parity checking takes place and all 32 bits of the received word remain unaltered. the hi-3593 subjects incoming arinc 429 messages to three different data filter checks before data is accepted. first all words are filtered for matching s/d bits, if enabled. secondly, the word label byte must match one of the three programmed priority-label match register values for the word to be stored in a priority-label register, and/or the label memory filter bit corresponding to the label must be set to a ?1? for the word to be stored in the receiver fifo. s/d filtering is enabled by setting the receive control register sdon bit to a ?1?. when enabled, bits 9 and 10 of the incoming arinc 429 word are compared with receive control register bits sd9 and sd10. if they match, the word is accepted for the next phase of filtering. if the bits do not match, the word is discarded and never stored. the s/d filtering function may be disabled by programming the sdon bit to a ?0?. when disbled, all incoming words are accepted for subsequent filtering. the three priority label registers store received data if the priority label feature is enabled, and the incoming arinc 429 word?s label byte matches the value stored in pririty-label match register #1, # 2 or #3. priority-label capture is enabled by setting the receive control register plon bit to ?1?. when plon = ?0? the priority-label feature is disabled and no arinc 429 words are stored in the priority-label registers. high speed low speed data bit rate min data bit rate max receiver parity received data acceptance and storage s/d filtering priority labels hi-3593 labrec arinc word sdon arinc word fifo matches bits 10, 9 enabled match sd10, sd9 label 0 x 0 x load fifo 1 no 0 x ignore data 1 yes 0 x load fifo 0 x 1 no ignore data 0 x 1 yes load fifo 1 yes 1 no ignore data 1 no 1 yes ignore data 1 no 1 no ignore data 1 yes 1 yes load fifo table 3. fifo loading control
receive data fifo following s/d filtering, accepted arinc 429 words are conditionally stored in the receive fifo. if label filtering is disabled, all words are stored. if label filtering is enabled, the incoming arinc429 word?s label byte value is checked against its corresponding bit in the pre-programmed label look-up table. if the bit is set to a ?1? the word is stored in the fifo. if the bit is a ?0? the word is not stored in the fifo. label recognition reading the label look-up table the user loads the 256-bit label look-up table to specify which 8-bit incoming arinc labels are stored in the receive fifo, and which are not. setting a ?1? in the look-up table enables processing of received arinc words containing the corresponding label. a ?0? in the look-up table causes discard of received arinc words containing the label. the 256-bit look-up table is loaded using spi op-codes 0x14 (receiver 1) and 0x28 (receiver 2), as described in table 1. after the look-up table is initialized, the control register bit labrec must be set to enable label recognition. all four bytes of the incoming arinc429 word are stored in the fifo. table 3. defines the rules for receive fifo loading. the contents of the label look-up table may be read via the spi interface using op-code 0x98 (receiver 1) or 0xb8 (receiver 2) as described in table 1. functional description (cont.) holt integrated circuits 11 hi-3593 retrieving data each time a valid arinc 429 word is loaded into the fifo, the receive fifo status register ffempty, ffhalf and fffull bits are updated. when the fifo is empty, the ffempty bit is a ?1? and ffhalf and fffull are ?0?. once the first received and accepted arinc 429 word is loaded into the fifo, ffempty goes low. each received arinc 429 word is retrieved via the spi interface using spi op-code 0xa0 (receiver 1) or 0xc0 (receiver 2). up to 32 arinc 429 words may be held in the receive fifo. fffull goes high when the receive fifo is full. failure to unload the receive fifo when full causes additional valid arinc 429 words to overwrite receive fifo location 32. a fifo half-full flag (ffhalf) is high whenever the receive fifo contains 16 or more words. the ffhalf bit provides a useful indicator to the host cpu that a sixteen word data retrieval routine may be performed. the ffempty, ffhalf or fffull status bits can also be output on the r1flag (receiver 1) and r2flag (receiver 2) pins. flag / interrupt assignment register bits 5, 4, 1 and 0 select which flag appears. additionally, a fifo not empty option may be programmed for the r1flag / r2flag pins causing the pin to go high any time at least one word is available in the fifo. figure 3. rec eiver block diagram word gap word gap timer bit clock end start error error detection shift register shift register null zeros shift register ones new word 32 bit shift register received arinc 429 word to filters (s/d, label, priority-label) parity check 32nd bit data eos sequence control 1mhz bit counter and end of sequence 1mhz 1mhz 1mhz
self test system operation dc/dc converter line driver operation if transmit control register bit selftest is equal ?1?, the transmitter serial output data is internally looped-back into the receiver 1. the data will appear inverted (compliment) on receiver 2. data passes unmodified from transmitter to receiver 1. setting transmit control register bit selftest to ?1? forces txaout and txbout to the null state to prevent self-test data from appearing on the arinc 429 bus. the receivers are independent of the transmitter. therefore, control of data exchanges is strictly at the option of the user. the only restrictions are: 1. the received data will be overwritten if the receive fifo is full and at least one location is not retrieved before the next complete arinc 429 word is received. 2. the transmit fifo can store 32 words maximum and ignores attempts to load additional data when full. the hi-3593 requires only a single +3.3v power supply. an integrated inverting / non-inverting voltage doubler generates the rail voltages (+/- 6.6v) which then power the line driver to produce the required +/- 5v arinc 429 signal levels. the internal dual-polarity charge pump requires four external capacitors, two for each polarity generated by the doubler. pins cp+ and cp- connect the external ?fly? capacitor, cfly, to the positive portion of the doubler, resulting in twice vdd at the v+ pin. an output ?hold? capacitor, cout, is placed between v+ and gnd. cout should be ten times the size of cfly. the inverting negative portion of the converter works in a similar fashion, with cfly and cout placed between cn+ / cn- and v- / gnd respectively (see block diagram page 2). note that capacitors rated for at least 10v should be used. v+/gnd=47 f v-/gnd=47 f cp+ / cp- = 0.47 f cn+ / cn- = 2.2 f the line driver in the hi-3593 directly drives the arinc 429 bus. the two arinc 429 outputs (txaout and txbout) provide a differential voltage to produce a +10v one, a -10v zero, and a 0 volt null. transmit control register bit rate controls both the transmitter data rate and the slope of the differential output signal. no additional hardware is required to control the slope. writing transmit control register bit rate to ?0? causes a 100 kbit/s data rate and a slope of 1.5 s on the arinc 429 outputs. setting rate to ?1? causes a 12.5 kbit/s data rate and a slope of 10s. slope rate is set by an on-chip resistor and capacitor and tested to be within arinc 429 specification requirements. low esr recommended values: functional description (cont.) holt integrated circuits 12 transmitter fifo operation data transmission transmitter parity figure 4 shows a block diagram of the hi-3593 transmitter. the transmit fifo is loaded with arinc 429 words awaiting transmission. spi op-code 0x0c writes each arinc 429 word into the fifo, at the next available fifo location. if transmit status register bit tfempty equals ?1? (fifo empty), then up to 32 words (32 bits each) may be loaded. if transmit status register bit tfempty equals ?0? then only the available positions may be loaded. if all 32 positions are full, transmit status register bit tffull is asserted. further attempts to load the transmit fifo are ignored until at least one arinc 429 word is transmitted. the transmit fifo half-full flag (transmit status register bit tfhalf) equals ?0? when the transmit fifo contains less than 16 words. when tfhalf equals ?0?, the system microprocessor can safely initiate a 16-word arinc 429 write sequence. in normal operation (transmit control register bit tparity = ?1?), the 32nd bit transmitted is an odd parity bit. if transmit control register bit parity equals ?0?, all 32 bits loaded into the transmit fifo are treated as data and are transmitted. the transmit and receive fifos may be cleared using software reset (spi op-code 0x44). the transmit fifo should be cleared after a self-test before starting normal operation to avoid inadvertent transmission of test data. if transmit control register bit tmode equals ?1?, arinc 429 data is transmitted immediately following the rising edge of the spi instruction that loaded data into the transmit fifo. writing transmit control register bit tmode to ?0? allows the software to control transmission timing; each time an spi op-code 0x40 is executed, all loaded transmit fifo words are transmitted. if new words are loaded into the transmit fifo before transmission stops, the new words will also be output. once the transmit fifo is empty and transmission of the last word is complete, the fifo can be loaded with new data which is held until the next spi 0x40 instruction is executed. once transmission is enabled, the fifo positions are incremented with the top register loading into the data transmission shift register. within 2.5 data clocks the first data bit appears at txaout and txbout. the 31 or 32 bits in the data transmission shift register are presented sequentially to the outputs in the arinc 429 format with the following timing: arinc data bit time 10 clocks 80 clocks data bit time 5 clocks 40 clocks null bit time 5 clocks 40 clocks word gap time 40 clocks 320 clocks a word counter detects when all loaded positions have been transmitted and sets the transmit status register tfempty bit high. the parity generator counts the ones in the 31-bit word. the 32nd bit transmitted will make parity odd. setting transmit control register bit tparity to ?0? bypasses the parity generator, and allows 32 bits of data to be transmitted. cs high speed low speed hi-3593
functional description (cont.) holt integrated circuits 13 line driver output pins line receiver input pins the hi-3593 txaout and txbout pins have 37.5 ohms in series with each line driver output, and may be directly connected to an arinc 429 bus. the alternate ampa and ampb pins have 5 ohms of internal series resistance and require external 32.5 ohm resistors at each pin. ampa and ampb are for applications where external series resistance is applied, typically for lightning protection devices. the line driver outputs txaout, txbout, ampa and ampb may be programmed to a high impedance state, allowing multiple line drivers to be connected to a single arinc 429 bus. to tri-state the outputs bit hiz in the transmit control register must be programmed to a ?1?. note that all other functions of the hi-3593 continue to operate as usual even though the outputs are tri-stated. the hi-3593 has two sets of line receiver input pins for each of the two receivers, rinxa/b and rinxa/b-40. only one pair may be used to connect to the arinc 429 bus. the unused pair must be left floating. the rinxa/b pins may be connected directly to the arinc 429 bus. the rinxa/b-40 pins require external 40k ohm resistors in series with each arinc input. these do not affect the arinc receiver thresholds. by keeping excessive voltage outside the device, this option is helpful in applications where lightning pro- tection is required. when using the rinxa/b-40 pins, each side of the arinc 429 bus hi-3593 must be connected through a 40k ohm series resistor in order for the chip to detect the correct arinc 429 levels. the typical 10 volt differential signal is translated and input to a window comparator and latch. the comparator levels are set so that with the external 40k ohm resistors, they are just below the standard 6.5 volt mini- mum arinc 429 data threshold and just above the standard 2.5 volt maximum arinc 429 null threshold. please refer to the holt an-300 application note for additional information and recommendations on lightning protection of holt line drivers and line receivers. master reset (mr) note: software reset only. application of a master reset from the mr pin or execution of opcode (0x04) causes immediate termination of data transmission and reception and clears the receive control registers, transmit control register, aclk and flag/interrupt registers to the default states. all fifos will be emptied and status flags are set to the default state (tfull is reset, tempty is set). reading an empty fifo may result in invalid data. opcode (0x044) clears the transmit and receive fifos and the priority-label registers all other registers are unaffected by software reset. tparity figure 4. transmitter block diagram data clock div[3:0] aclk parity generator data and null timer sequencer line driver bit and word gap counter start sequence word counter and fifo control increment word count data clock divider fifo loading sequencer txaout txbout 32 x 32 fifo 32 bit parallel load shift register bit clock word clock address load tffull hiz tfhalf tfempty spi interface sck cs si so spi commands spi commands
hi-3593 holt integrated circuits 14 serial peripheral interface (spi) basics cpol- cpha a rising edge on chip select terminates the serial transfer and reinitializes the hi-3593 spi for the next transfer. if goes high before a full byte is clocked by sck, the incomplete byte clocked into the device si pin is discarded. in the general case, both master and slave simultaneously send and receive serial data (full duplex), per figure 5 below. however the hi-3593 operates half duplex, maintaining high impedance on the so output, except when actually transmitting serial data. when the hi-3593 is sending data on so during read operations, activity on its si input is ignored. figures 6 and 7 show actual behavior for the hi-3593 so output. cs cs cs cs the hi-3593 uses an spi synchronous serial interface for host access to internal registers and data fifos. host serial communication is enabled through the chip select ( ) pin, and is accessed via a three-wire interface consisting of serial data input (si) from the host, serial data output (so) to the host and serial clock (sck). all read / write cycles are completely self-timed. the spi (serial peripheral interface) protocol specifies master and slave operation; the hi-3593 operates as an spi slave. the spi protocol defines two parameters, cpol (clock polarity) and cpha (clock phase). the possible combinations define four possible "spi modes". without describing details of the spi modes, the hi-3593 operates in mode 0 where input data for each device ( master and slave) is clocked on the rising edge of sck, and output data for each device changes on the falling edge (cpha = 0, cpol = 0). be sure to set the host spi logic for mode 0. as seen in figure 5, spi mode 0 holds sck in the low state when idle. the spi protocol transfers serial data as 8-bit bytes. once chip select is asserted, the next 8 rising edges on sck latch input data into the master and slave devices, starting with each byte?s most-significant bit. the hi-3593 spi can be clocked at 10 mhz. multiple bytes may be transferred when the host holds low after the first byte transferred, and continues to clock sck in multiples of 8 clocks. cs serial peripheral interface msb lsb msb lsb high z high z cs so si 01234567 sck (spi mode 0) figure 5. generalized single-byte transfer using spi protocol modes 0
hi-3593 holt integrated circuits 15 hi-3593 spi commands for the hi-3593, each spi read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion of . since hi-3593 command byte reception is half-duplex, the host discards the dummy byte it receives while serially transmitting the command byte. figures 6 and 7 show read and write timing as it appears for a single-byte and dual-byte register operation. the command byte is immediately followed by a data byte comprising the 8-bit data word read or written. for a single register read or write, is negated after the data byte is transferred. multiple byte read or write cycles may be performed by transferring more than one byte before is negated. table 1. defines the required number of bytes for each instruction. note: spi instruction op-codes not shown in table 1 are ?reserved? and must not be used. further, these op-codes will not provide meaningful data in response to read commands. cs cs cs cs two instruction bytes cannot be ?chained? ; must be negated after the command, then reasserted for the following read or write command. figure 6. single-byte read from a register cs so si sck msb lsb 0 12 3 4 5 67 high z high z 0 12 3 4 5 67 msb lsb msb lsb data byte op-code byte host may continue to assert here to read sequential word(s) when allowed by the instruction. each word needs 8 sck clocks. cs host serial peripheral interface, cont. figure 7. 2-byte write example cs so si sck spi mode 0 msb lsb 0 12 3 4 5 67 high z 0 12 3 4 5 670 12 3 4 5 67 msb lsb msb lsb data byte 0 data byte 1 op-code byte host may continue to assert here to write sequential byte(s) when allowed by the spi instruction. each byte needs 8 sck clocks. cs
receiver operation flags (1) arinc data cs si bit 31 bit 32 rflg t arinc bit 32 spif t so spi instruction (e.g. 0xa0) arinc bit 31 arinc bit 30 rxr t data rate - example pattern txaout arinc bit txbout null data data data null null word gap bit 1 next word bit 32 bit 31 bit 30 serial output timing diagram cs sck so chz t hi impedance sckh t t dv lsb cph t t sckl msb hi impedance serial input timing diagram cs sck si chh t ceh t msb ces t ds tt dh lsb cph t sckr t sckf t timing diagrams arinc bit 1 holt integrated circuits 16 ces t cyc t cyc t hi-3593 (1) receiver status flag outputs: r1flag, r2flag, mb1-1, mb1-2, mb1-3, mb2-1, mb2-2, mb2-3 r1int / r2int t intw
timing diagrams (cont.) holt integrated circuits 17 hi-3593 transmitting data cs si spi instruction 0x0c spi instruction 0x40 tflg t tempty / tfull datt t sdat t aout bout arinc bit arinc bit arinc bit aout bout diff v (aout - bout) +5v +5v +5v +10v +10v -10v -5v -5v -5v data bit 1 data bit 2 data bit 32 one level zero level null level 90% 90% 10% 10% t fx t rx t fx t rx output waveforms
holt integrated circuits 18 hi-3593 supply voltages v ......................................... -0.3v to +5.0v v+ ......................................................... +7.0v v- ......................................................... -7.0v voltage at pins rinxx-xx .................................. -120v to +120v voltage at pins txaout, txbout, ampa, ampb ......... v- to v+ voltage at any other pin ............................... -0.3v to v +0.3v solder temperature (reflow).............................................. 260 dd dd c power dissipation at 25c plastic quad flat pack ............... 1.5 w, derate 10mw/ c dc current drain per digital input pin ........................... 10ma operating temperature range (industrial): ..... -40c to +85c (extended): ..... -55c to +125c storage temperature range ........................ -65c to +150c note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings the hi-3593pcx uses a 44-pin plastic chip-scale package. this package has a metal heat sink pad on its bottom surface. this heat sink is electrically isolated from the die. to enhance thermal dissipation, the heat sink can be soldered to matching circuit board pad. heat sink - chip-scale package only
arinc 429 outputs - pins txaout, txbout, (or ampa, ampb with external 32.5 ohms) logic outputs operating voltage range operating supply current output voltage: logic "1" output voltage v i = -100 a v logic "0" output voltage v i = 1.0ma v output current: output sink i v = 0.4v 1.6 ma output source i v = v - 0.4v -1.0 ma output capacitance: c 15 pf v 3.15 3.45 v transmitting data in high-speed mode. i outputs unloaded 50 ma transmitting data in high-speed mode. i 400 ohm differential output load 75 ma arinc output voltage (ref. to gnd) one or zero v no load and magnitude at pin, 4.50 5.00 5.50 v null v -0.25 0.25 v arinc output voltage (differential) one or zero v no load and magnitude at pin, 9.0 10.0 11.0 v null v -0.5 0.5 v arinc output current i momentary short-circuit current 80 ma dout nout ddif ndif out oh oh ol ol ol out oh out dd o dd 90%vdd 10% vdd dd ddl limits parameter conditions unit symbol differential input voltage: one v common mode voltages 6.5 10.0 13.0 v (rin1a to rin1b, rin2a to rin2b) zero v less than 25v with -13.0 -10.0 -6.5 v null v respect to gnd -2.5 0 2.5 v input resistance: differential r - 140 - k to gnd r - 140 - k to v r - 100 - k input current: input sink i 200 a input source i -450 a input capacitance: differential c 20 pf (guaranteed but not tested) to gnd c 20 pf to v c 20 pf input voltage: input voltage hi v v input voltage lo v v input current: input sink i 1.5 a input source i -1.5 a min typ max arinc 429 inputs - pins rin1/2a, rin1/2b, rin1/2a-40 (with external 40kohms), rin1/2b-40 (with external 40kohms) logic inputs ih il nul i g dd h ih il i g dd h ih il ih il (rinxa to rinxb) pull-down current (mr, si, sck, aclk pins) i 60 a pull-up current ( pin) i -60 a 80% vdd 20% vdd pd pu cs v = 3.3v, ta = operating temperature range (unless otherwise specified). dd dc electrical characteristics holt integrated circuits 19 hi-3593
limits parameter symbol units min typ max spi interface timing receiver timing sck clock period active after last sck rising edge t 10 ns setup time to first sck rising edge t 10 ns hold time after last sck falling edge t 10 ns inactive between spi instructions t delay - last bit of received arinc word to receive flag change - hi speed t 16 s received data available to spi interface. rxflag to active spi receiver read fifo instruction to rxflag t 0 spi transmit data write (fifo flag empty or full) t line driver transition differential times: high to low t 1.0 1.5 2.0 t 100 ns 55 ns spi si data set-up time to sck rising edge t 10 ns spi si data hold time after sck rising edge t 10 ns sck rise time t 10 ns sck fall ime t 10 ns sck pulse width high t 20 ns sck pulse width low t 25 ns so valid after sck falling edge t 35 ns so high-impedance after sck falling edge t 30 ns mr pulse width t 50 ns delay - last bit of received arinc word to receive flag change - lo speed t 126 s t0 ns tns rxint pulse width t 500 ns 0ns fifo flag delay after enable transmit instruction - hi speed t 2 s fifo flag delay to arinc 429 data output - hi speed t 40 s fifo flag delay to arinc 429 data output - lo speed t 320 s high speed s low to high t 1.0 1.5 2.0 s low speed high to low t 5.0 10 15 s low to high t 5.0 10 15 s cyc cph ds dh sckr sckf sckh sckl dv chz rflg rxr datt sdat sdat rx fx rx cs cs cs cs cs chh ces ceh rflg spif tflg fx mr cyc int transmitter timing ac electrical characteristics vdd = 3.3v, ta = operating temperature range and fclk=1mhz 0.1% + limits parameter test conditions units min typ max symbol start-up transient (v+, v-) operating switching frequency f - 650 - khz worst case maximum voltage doubler output v - 6.93 v dc/dc converter capacitor recommendations. for optimum performance use typical (not min.) values. for emc compliance, see an-135. c and c caps are ceramic or tantalum, preferably multilayer, non polarized dielectric xr7, 10v minimum. c cap is tantalum 10v minimum. t--10ms v ratio of bulk storage to fly-back capacitors c c 2.2 10 fly-back capacitor c c / c >= 10 1.0 4.7 - f c [0.5, 1.0] mhz 500 m bulk storage capacitor c c / c >= 10 2.2 4.7 - f c [0.5, 1.0] mhz 300 m by-pass capacitor c c >= c (connect from v to gnd) start dd = 3.6v t= -55c open load out / fly fly fly out out sw dd2+(max) fly out supply out fly (esr) out fly (esr) supply supply out dd converter characteristics v = +3.3v, t = operating temperature (unlesss otherwise stated) dd a holt integrated circuits 20 hi-3593
ordering information hi - 3593 xx x x package description 44 pin plastic chip-scale, qfn (44pcs) part number pc 44 pin plastic quad flat pack, pqfp (44ptqs) pq lead finish part number 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank temperature range burn in -40c to +85c no -55c to +125c no t part number t i flow i holt integrated circuits 21 hi-3593 -55c to +125c yes m m
revision history p/n rev date description of change ds3593 new 02/03/08 initial release a 08/11/11 modified ac electrical characteristics for 10 mhz spi operation. b 08/13/13 updated dc/dc converter section. added converter characteristics section to ac electrical characteristics. corrected description for op codes 0x14 and 0x28 in table 1. clarified solder reflow temperature. holt integrated circuits 22 hi-3593
hi-3593 package dimensions 44-pin plastic chip-scale package (qfn) package type: 44pcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .203 .006 (5.15 .15) .016 .002 (0.40 .05) .010 (0.25) .020 (0.50) .008 (0.2) .039 (1.00) .276 (7.00) bsc .203 .006 (5.15 .15) typ typ bottom view top view bsc .276 (7.00) bsc max inches (millimeters) package type: 0 7 detail a see detail a sq. 44ptqs 44-pin plastic quad flat pack (pqfp) .006 (.15) .547 .010 (13.90 .25) .394 .004 (10.0 .10) sq. max. .014 ..002 (.35 .05) .035 .006 (.88 .15) .005 (.13) r min. .012 (.30) r max. .055 .002 (1.4 .05) .063 (1.6) max. .0315 (.80) inches (millimeters) bsc bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) holt integrated circuits 23

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